1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and more particularly, to a semiconductor integrated circuit device containing a protection circuit that is composed of at least one Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with the Lightly Doped Drain (LDD) structure.
2. Description of the Prior Art
Recently, a semiconductor integrated circuit device has been becoming denser and electronic components provided therein have been becoming finer. In response to this trend, impurity-doped regions such as source/drain regions of an MOSFET have been formed shallower within a semiconductor layer or substrate, making the sheet resistance of the impurity-doped regions higher. Such the high sheet resistance of the impurity-doped regions affects the operation of the component including the regions and as a result, some problems occur regarding their high-speed operation occur.
To cope with the above problems, a sheet-resistance reduction technique has been developed and used practically, in which the surface areas of the silicon impurity-doped regions are silicided to form refractory-metal silicide layers on the respective impurity-doped regions.
FIG. 1 shows a partial cross section of an MOSFET provided in a conventional semiconductor integrated circuit device, which is produced by using the conventional sheet-resistance reduction technique.
As shown in FIG. 1, a gate oxide layer 22 is selectively formed on a p-silicon substrtate 21. A gate electrode 23 made of a conductive material such as polysilicon is selectively formed on the gate oxide layer 22. Sidewall spacers 25a and 25b are formed on the substrate 21 at each side of the gate electrode 23.
On one side of the gate electrode 23, an n.sup.- -diffusion region 24a that is lightly doped with an n-impurity and an n.sup.+ -diffusion region 26a that is heavily doped with an n-impurity are formed in the surface area of the substrate 21. The n.sup.- -diffusion region 24a extends to an opposing end of the gate electrode 23. The n.sup.+ -diffusion region 26a extends to the outer end of the sidewall spacer 25a and is placed on the region 24a. The diffusion regions 24a and 26a constitute a source region of an MOSFET.
On the other side of the gate electrode 23, an n.sup.- -diffusion region 24b that is lightly doped with an n-impurity and an n.sup.+ -diffusion region 26b that is heavily doped with an n-impurity are formed in the surface area of the substrate 21. The n.sup.- -diffusion region 24b extends to an opposing end of the gate electrode 23. The n.sup.+ -diffusion region 26b extends to the outer end of the sidewall spacer 25b and is placed on the region 24b. The diffusion regions 24b and 26b constitute a drain region of the MOSFET.
To reduce the sheet resistance of the source and drain regions, refractory-metal silicide layers 27a and 27b are formed on the n.sup.+ -diffusion regions 26a and 26b, respectively. The silicide layer 27a is placed on the entire region 26a and the silicide layer 27b is placed on the entire region 26b.
An interlayer insulator film 28 is formed over the substrate 21 to cover the MOSFET. A patterned interconnection film 30 made of aluminum or the like is formed on the interlayer insulator film 28. The interconnection film 30 is contacted with the silicide layer 27a of the source region through contact holes 29a formed in the film 28 to be electrically interconnected with the source region. The interconnection film 30 is contacted with the silicide layer 27b of the drain region also through contact holes 29b formed in the film 28 to be electrically interconnected with the drain region.
Thus, the MOSFET employs the LDD structure and the above sheet-resistance reduction technique.
Typically, a semiconductor integrated circuit device includes internal circuits for producing specified functions, and input/output (I/O) circuits through which input signals are supplied into the internal circuits and output signals are derived therefrom. Also, the I/O circuits typically contain protection circuits to protect the internal circuits from the electrostatic discharge (ESD).
With a conventional MOS semiconductor integrated circuit device, a plurality of MOSFETs having the structure of FIG. 1 are employed in not only the internal circuits and the I/O circuits but also the protection circuits. When the MOSFET of FIG. 1 is employed in the protection circuit, in other words, it is used as a protection transistor, since the protection MOSFET has the silicide layers 27a and 27b on the source and drain regions 24a and 24b, the protection MOSFET has a lower resistance of the source and drain regions than the case of no such silicide layers. As a result, the conventional protection MOSFET exhibits a V-I characteristic as shown by the curve O-A-B-C in FIG. 2.
Specifically, when the gate electrode 23 is applied with a constant voltage of V.sub.G, the relationship between the drain current I.sub.D and the source-drain voltage V.sub.SD is expressed by the curve O-A-B-C. Within the "normal operation region" between the points O and A, the drain current I.sub.D increases linearly and gradually from the point O to the point A together with the increasing source-drain voltage V.sub.SD. At the point A (V.sub.SD =V.sub.A), the source-drain voltage V.sub.SD starts to decrease in spite of the increase of the drain current I.sub.D. The region from the point A to the point B is the "snapback region" in which the MOSFET exhibits a negative resistance characteristic.
At the point B (V.sub.SD =V.sub.B &gt;V.sub.A), the source-drain voltage V.sub.SD starts to increase again toward the point C together with the increase of the drain current I.sub.D. The region from the point B to the point C is the "breakdown region". At the point C (V.sub.SD =V.sub.C, I.sub.D =I.sub.C) the p-n junction of the drain region is electrostatically broken or damaged, which means damage to the MOSFET.
The snapback voltage V.sub.SD is shown as V.sub.A in FIG. 2. However, the voltage V.sub.SB tends to vary from place to place within the same MOSFET due to the fluctuation in fabrication. For example, V.sub.SB =V.sub.A in one place and V.sub.SB =V.sub.A ' in another place where V.sub.A &lt;V.sub.A '.
If V.sub.C &lt;V.sub.A as shown in FIG. 2, even if the snapback phenomenon occurs in the place where V.sub.SB =V.sub.A, the snapback phenomenon does not occur in the place where V.sub.SB =V.sub.A '. Therefore, the drain current I.sub.D flows through only the snapbacked place where V.sub.SB =V.sub.A and as a result, the p-n junction is damaged partially in the snapbacked place, leading to damage of the MOSFET itself. This means the decrease in the substantial breakdown voltage.